RELATED PATENT APPLICATIONS
Attorney's Docket Number TSMC97-126, "A Novel Method to Erase A Flash EEPROM Using Negative Gate Source Erase Followed By A High Negative Gate Erase," Ser. No.: 08/928,227, Filing Date: Sep. 12, 1997, assigned to the Same Assignee as the present invention.
Attorney's Docket Number TSMC97-109, "A Mixed Mode Erase Method To Improve Flash EEPROM Write/Erase Threshold Closure," Ser. No.: 08/907,984, Filing Date: Aug. 11, 1997, assigned to the Same Assignee as the present invention.
Attorney's Docket Number TSMC97-085, "A Bi-Modal Erase Method For Eliminating Cycling-induced Flash EEPROM Cell Write/Erase Threshold Closure," Ser. No.: 081927,472, Filing Date: Sep. 11, 1997, assigned to the Same Assignee as the present invention.
Attorney's Docket Number TSMC97-099, "A Novel Erase Method Of Flash EEPROM By Using Snapback Characteristic," Ser. No.: 08/957,678, Filing Date: Oct. 24, 1997, assigned to the Same Assignee as the present invention.
1. Field of the Invention
This invention relates generally to a class of non-volatile memory devices referred to as flash electrically erasable programmable read-only memory (flash EEPROM). More particularly, this invention relates to methods and means to erase digital data from a flash EEPROM cell and for eliminating trapped charges from the flash EEPROM cell.
2. Description of Related Art
The structure and application of the flash EEPROM is well known in the art. The Flash EEPROM provides the density advantages of an erasable programmable read-only memory (EPROM) that employs ultraviolet light to eliminate the programming with the speed of a standard EEPROM. FIG. 1 illustrates a cross-sectional view of a flash EEPROM cell of the prior art. The flash EEPROM cell 10 is formed within a p-type substrate 12. An n.sup.+ drain region 14 and an n.sup.+ source region 18 is formed within the p-type substrate 12.
A relatively thin gate dielectric 36 is deposited on the surface of the p-type substrate 12. The thin gate dielectric 36 will also be referred to as a tunnel oxide, hereinafter. A poly-crystalline silicon floating gate 32 is formed on the surface of the gate dielectric 36 above the channel region 34 between the drain region 14 and source region 18. An interpoly dielectric layer 30 is placed on the floating gate 32 to separate the floating gate 32 from a second layer of poly-crystalline silicon that forms a control gate 28.
A p.sup.+ diffusion 16 is placed in the p-type substrate 12 to provide a low resistance path from a terminal 20 to the p-type substrate. The terminal 20 will be attached to a substrate voltage generator Vsub. In most application of an EEPROM, the substrate voltage generator Vsub will be set to the ground reference potential (0V).
The source region 18 will be connected to a source voltage generator VS through the terminal 22. The control gate 28 will be connected through the terminal 26 to the control gate voltage generator VG. And the drain region 14 will be connected through the terminal 24 to the drain voltage generator VD.
According to conventional operation, the flash EEPROM cell 10 is programmed by setting the gate control voltage generator VG to a relatively high voltage (on the order of 10V). The drain voltage generator VD is set to a moderately high voltage (on the order of 5V), while the source voltage generator VS is set to the ground reference potential (0V).
With the voltages as described above, hot electrons will be produced in the channel 34 near the drain region 14. These hot electrons will have sufficient energy to be accelerated across the gate dielectric 36 and trapped on the floating gate 32. The trapped hot electrons will cause the threshold voltage of the field effect transistor (FET) that is formed by the flash EEPROM cell 10 to be increased by three to five volts. This change in threshold voltage by the trapped hot electrons causes the cell to be programmed.
During the programming process some of the hot electrons will be trapped 42 in the tunnel oxide 36 or in surface states 40 at the surface of the p-type substrate 12. These hot electrons will cause the reduction of the transconductance value and prvent channel hot electrons from injecting into the floating gate 32 during further programming steps. Therefore, the threshold voltage will decrease as cycling time increases.
To erase the flash EEPROM cell 10, as shown in FIG. 2, a positive voltage (on the order of 10V) is generated by the source voltage generator VS. The control gate voltage generator VG and the substrate voltage generator VS are set to the ground reference potential. The drain voltage generator VD is usually disconnected from the terminal 24 to allow the drain region 14 to float. Under these conditions there is a large electric field developed across the tunnel oxide 36 in the source 18 and floating gate 32 overlap region. This field causes the electrons trapped in the floating gate 32 to flow to portion of the floating gate 32 that overlaps the source region 18. The electrons are then extracted to the source region 18 by the Fowler-Nordheim tunneling.
During the erasure process, some positive charges 38 that result from band-to-band tunneling, will be forced and trapped in the tunnel oxide 36. These trapped positive charges will act as trapping centers which cause the erase threshold voltage to decrease when the holes are trapped the begining of the cycling and make the threshold voltage increase when electrons are trapped instead of the hole. As can be shown in FIG. 3, the combination of the decrease 52 in the programmed threshold voltage 50 and the increase 57 in the erased threshold voltage 55 will cause the separation of the programmed threshold voltage 50 and the erased threshold voltage 55 to close until the flash EEPROM cell 10 fails. At this time the flash EEPROM will no longer be able to operate reliably to store digital data.
U.S. Pat. No. 5,481,494 (Tang et al.) shows a method for tightening the threshold voltage V.sub.T distribution of an array of flash EEPROM cells. A relatively low positive voltage is applied to the source regions of the array of flash EEPROM cells and a negative voltage is applied to the control gate and lowered to a predetermined value during the erase cycle. This will insure a tighter distribution of the thresholds of the array of cells. The value of a load resistor between the low positive voltage and the source region is simultaneously reduced to a predetermined value so as to compensate for the increased erase time caused by the lowering of the magnitude of the negative constant voltage.
U.S. Pat. No. 5,485,423 (Tang et al.) describes a method of erasure of a flash EEPROM. A relatively low positive pulse voltage is applied to the source region of the flash EEPROM cell during the erase cycle. Simultaneously, a negative ramp voltage is applied to the control gate of the flash EEPROM. This will achieve an averaging of the tunneling field during the entire erase cycle.
U.S. Pat. No. 5,521,866 (Akaogi) describes a non volatile semiconductor memory device having a floating gate. The memory device is constructed with two wells diffused into the semiconductor substrate. The source and drain are then diffused into the second well with a floating gate and control gate disposed on the surface of the semiconductor substrate much as described in FIG. 1. The erasure process involves applying a positive voltage to each of the two wells.
U.S. Pat. No. 5,231,602 (Radjy et al.) describes a method of erasing a flash EEPROM cell by controlling the electric field across the tunnel oxide. The drain is connected through a variable resistor to a programming voltage source and a variable voltage source is connected to the source. The variable voltage source is adjusted between 0 and 5V, while the programming voltage source is set between 5V and 20V. The tunneling current is optimized by adjustment of the variable resistor and the variable voltage.